Semiconductor memory devices constitute an essential part of computer systems due to the relatively high access speeds obtainable and the generally low cost of such devices. One type of semiconductor memory device that is particularly advantageous is the dynamic random access memory (DRAM), which provides a relatively high memory density while also providing the lowest cost per bit of any memory device currently available. DRAMs include a single transistor and capacitor for each memory cell in a conventional memory cell array structure. Briefly, and in general terms, a logic state is stored in each memory cell of a DRAM by maintaining the capacitor in a charged state corresponding to a logic ‘1’ state, or in a discharged state, corresponding to a logic ‘0’ state. The transistor is operatively coupled to the capacitor and acts as a switch to control the charging and discharging of the capacitor. Since the capacitor may lose charge through capacitor leakage, a particular shortcoming present in DRAM devices is that the charge on the capacitor must be periodically refreshed in order to maintain an acquired logic state.
Since DRAMs generally provide high memory density, DRAMs usually require a package having a relatively large number of pins in order to communicate signals from the DRAM to external circuits. For example, in a 32 Mb×4 DRAM device, 25 address lines and four data input/output pins are required. In addition, other pins are also required for the operation of the DRAM memory device, including row address strobe (RAS) and column address strobe (CAS) pins, a write enable (WE) pin, and power supply and ground connection pins (Vcc and Vss), among other pins. Since the number of pins generally adversely affects the size of the DRAM device package, and correspondingly increases the amount of “real estate” required on a supporting circuit board, if one or more device pins present on a device package are not used, it would be advantageous to reconfigure the pin so that it may be used for a different purpose. For example, a number of DRAM devices include a data mask (DM) pin, which is not used in certain DRAM devices.
One possible use for an unused memory device pin that is to communicate a temperature value associated with the memory device to an external controller. For example, it has been observed that the refresh time for a DRAM memory cell varies inversely in proportion to the temperature of the cell, so that as the memory cell increases in temperature, it will require more frequent refreshment. Typically, the memory cell is refreshed at a frequency that corresponds to the highest cell temperature anticipated in service. As a result, if the memory cell operates at temperature that is significantly lower than the highest anticipated temperature, it will be refreshed more frequently than necessary. Since the time consumed by refresh operations decreases the time available for accessing information stored in the memory device, memory devices that are refreshed more frequently than necessarily generally decrease the operating speed of systems using the memory device.
Another possible use for an unused memory device pin is to communicate parity check information from the memory device to an external circuit. Briefly, parity is an error detection procedure that is used to verify the integrity of digital data following a read operation. In general, a parity check includes appending an additional parity bit to each byte that reflects the number of ones present in the byte, which may be either even or odd. The parity check then proceeds by reading the byte and generating a new parity bit. The newly generated parity bit may then be compared to the parity of the bit appended to the byte. If the generated bit and the appended bit do not favorably agree, an error is indicated.
Still another possible use for an unused memory device pin is to communicate system channel information from a memory device to an external circuit. In general, before a read or write operation occurs in a memory device, the device receives a plurality of control signals in synchronization with pulses from a system clock. In response, a read or write operation occurs so that data is transferred in synchronization with the clock and within a prescribed data window, or “data eye”. In many cases, however, data may at least partially drift outside the data eye due to signal reflection, inductive cross talk between adjacent signal lines, variations in supply voltage, and noise due to thermal or other effects.
As a result, there is a need to provide a way to reconfigure selected pins on a semiconductor memory device to transfer data of various types. In particular, pins that are extraneous or otherwise unused on existing microelectronic memory devices may advantageously reconfigured to accomplish this purpose.